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Custom SoC (ASIC)

Design Technology

PCB co-design

PCB co-design

Socionext achieves perfect operation on the first attempt through LSI development based on the chip, package, and PCB co-design flow. While offering a good forecast for design through reference design, we develop and improve LSI models (IBIS, timing model, LSI power supply model) necessary for transmission line analysis of DDR4 and other memory interfaces and USB3.0 and other SerDes interfaces to achieve total optimization in each phase of design based on integrated chips, packages, and PCB analysis. This allows for an issue that used to only be discovered in the actual design phase to be addressed in the prototyping phase.

PCB co-design

Analysis

We offer customers IBIS and a timing model early on in the design stage so that they can conduct transmission line analysis taking timing into account.

PCB co-design02

The use of IBIS5.0 and an LSI power supply model (chip and package) for PCB power supply impedance analysis and SSO noise analysis allows customers to perform high accuracy development in a short TAT.

PCB co-design03

Simulation

Utilizing advanced simulation technologies, we offer the best package solution.

●Mechanism simulation

Incorporating mechanism simulation into package design allows customers to propose high reliability packages.

[Case: Stress Analysis of Solder Joint Sections]

●Thermal design simulation

By combining actual measurement of thermal resistors and thermofluid simulation, we perform high accuracy thermal resistance analysis reproducing the operating environment of products. Analysis in an environment defined by the JEDEC standard is also possible.

●Thermal resistance measurements

Measurement of transient thermal resistance values in accordance with the JEDEC standard JESD51-14 is possible.

Products / Services

Custom SoC (ASIC)

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Custom SoC
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Introduction Video

Socionext’s Custom SoC Solution
(YouTube)
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