Video Codec Subsystem
Due to an imbalance between the advance of DDR memory to the ultra-high speed generation along with an increase in the burst length and access by video codec processes handling small size rectangular image data to the DDR, a reduction in the efficiency of using the DDR memory band width has become an issue. This subsystem enables high efficiency video codec processing that can save the band width using Socionext’s unique technology.
We have developed our unique bus protocol methodology that can improve memory access efficiency in the codec process without being significantly affected by advances in DDR. Tightly coupling our codec engine and our memory controller with the methodology enables the memory controller to efficiently access DRAM by taking into account a physical memory map based on the 2D information on image data accessed by the codec engine, reducing the required memory band width significantly.
Achieves HEVC codec processing with a smaller bus width (bit) as listed below.
[Example: When using LPDDR4 2400 Mbps]