Socionext will present at 2025 TSMC North America OIP Ecosystem Forum
Socionext will present at 2025 TSMC North America OIP* Ecosystem Forum in Santa Clara, CA, USA on Wednesday, September 24, 2025.
At this forum, Socionext and Synopsys will jointly present their initiatives and achievements in developing the 3DIC test chip, which integrates dies from different processes. In addition, Socionext will jointly present its power management efforts for SoCs and chiplets in collaboration with Analog Bits, an IP vendor.
*:OIP: Open Innovation PlatformEvent Information
| Title | 2025 TSMC North America OIP Ecosystem Forum |
|---|---|
| Date/Time | Wednesday, September 24, 2025 8:30 to 18:00 (Pacific Time) |
| Venue | Santa Clara Convention Center (Santa Clara, CA, USA) |
| Organizer | Taiwan Semiconductor Manufacturing Company Limited |
Socionext Presentation
●Session : Automotive, IoT & RF Track
| Title | Pinless PLL, PVT Sensor and Power Supply Spike Detectors for Datacenter, AI and Automotive Applications - Analog Bits and Socionext |
|---|---|
| Date/Time | Wednesday, September 24, 2025 11:30 to 11:50 (Pacific Time) |
| Speaker | Paul Little Director, Technical Marketing, Socionext America Inc. |
●Session : HPC & 3DIC Track
| Title | Accelerating SOIC-X 3D-Stacked Advanced Package Design: From Architecture Planning and Optimization to Tapeout |
|---|---|
| Date/Time | Wednesday, September 24, 2025 13:30 to 13:50 (Pacific Time) |
| Speaker | Srinivas Kukutla Director, Methodology & Physical Design, Socionext America Inc. |