Socionext will present at SNUG Silicon Valley
Socionext will give two presentations at "SNUG Silicon Valley," which will be held from Wednesday, March 11 to Thursday, March 12, 2026.
In these presentations, Socionext will highlight its initiatives to achieve highly accurate clock-waveform quality in high-speed and large-scale chips, as well as the development activities and results of a 3DIC test chip that integrates dies fabricated using different process technologies.
Event Information
| Title | SNUG Silicon Valley |
|---|---|
| Period | Wednesday, March 11 to Thursday, March 12, 2026 |
| Venue | Santa Clara Convention Center (Santa Clara, California, USA) |
| Organizer | Synopsys, Inc. |
Socionext Presentation
●Session : Technical Session / Signoff
| Date/Time | Wednesday, March 11, 2026 12:10 PM to 12:40 PM (Local Time) |
|---|---|
| Venue | Hall D |
| Title | PrimeClock: Comprehensive Clock Integrity Analysis Solution for Large-Scale Product Designs |
| Speaker | Akira Katakami Engineer, Advanced Technology Unit, Global Leading Group, Socionext Inc. |
●Session : Technical Session / Multi-Die Design
| Date/Time | Wednesday, March 11, 2026 2:35 PM to 3:05 PM (Local Time) |
|---|---|
| Venue | Hall A2 |
| Title | Achieving TSMC-SoIC® 3DIC Tapeout with a Production-Ready Exploration-to-Signoff Methodology |
| Speaker | Srinivas Kukutla Director, Methodology & Physical Design, Socionext America Inc. |