Socionext presented at the 40th Spring Conference of the Japan Institute of Electronics Packaging (JIEP).
Socionext delivered a presentation at the 40th Japan Institute of Electronics Packaging (JIEP) Spring Conference, which was held from Tuesday, March 10 to Thursday, March 12, 2026.
In this presentation, the company highlighted its power integrity technologies for advanced package designs supporting next-generation AI, HPC, and ADAS applications.
Event Information
| Title | The 40th Japan Institute of Electronics Packaging (JIEP) Spring Conference (Japanese only) |
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| Period | Tuesday, March 10 to Thursday, March 12, 2026 |
| Venue | Tokyo Tama Mirai Messe (Hachioji-city, Tokyo) |
| Organizer | The Japan Institute of Electronics Packaging (JIEP) |
Socionext Presentation
●Session : [11B1] Circuit and Packaging Design Technology & High-Speed, High-Frequency, and Electromagnetic Characteristics Technology 6
| Date/Time | Wednesday, March 11, 2026 10:30 AM to 10:45 AM (JST) |
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| Venue | Room B (3rd Floor, Conference Room 1) |
| Title | Balancing PDN Current Density in Ultra-High Current SoCs through Packaging Design Optimization |
| Speaker | Narimasa Takahashi Principal Engineer, Package Development Division, Development Group, Socionext Inc. |