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Custom SoC (ASIC)

Design Technology

Front-end Design

Front-end Design

We offer a development environment using standard EDA tools as a SoC development environment for customers and a tool we created for improving design efficiency as a design kit. The front-end design kit, which is uniquely optimized by Socionext, enables the development of high performance, small chip size, low power LSIs.

[Front-end design kit(EDA tools)]
High level synthesis Catapult*3, C-to-Silicon Compiler*1, Stratus*1
RTL style check SpyGlass*2
Functional verification Verilog-HDL Incisive Enterprise Simulator*1, Questa*3, VCS-MX,VCS*2
VHDL Incisive Enterprise Simulator*1, Questa*3, VCS-MX*2
CPF/UPF Incisive Enterprise Simulator-XL*1, Questa*3, VCS-NLP*2
Logic synthesis Design Compiler*2, Encounter RTL Compiler*1, Genus Synthesis Solution*1
Equivalence verification Encounter Conformal Equivalence Checker*1, Formality*2
Timing constraint verification Encounter Conformal Constraint Designer*1, SpyGlass Constraints*2
MV verification Encounter Conformal Lowpower*1, VC Static Low Power*2
Analysis/debugger Verdi*2
Netlist check*4 SpyGlass*2
Pre-DFT check*4 SpyGlass DFT*2

*1:Cadence, Inc.
*2:Synopsys, Inc.
*3:Mentor Graphics Co.
*:We provide a checker we developed in-house to suit the technology.

Design Specification Interface

Designing an SoC requires not only RTL and netlist as logic design data, but the power intent, such as the SDC describing timing specifications including clock frequency, and CPF/UPF containing power supply specifications, including power gating design and multi-power/multi voltage design. We provide interface files in our unique format for such SDC and power intent. Using such files allows you to improve efficiency in writing and reviewing specifications and quickly verify the consistency between the handed-off RTL, power supply specifications, and timing specifications as well as layout compatibility.

Physical aware Logic synthesis

Due to progress in technology, logic design that takes layout into account is becoming important for improving SoC design efficiency as well as optimizing area and timing. For this reason, we adopt physical aware synthesis that performs optimization by taking the actual layout into account. Through this co-design between the logic design and layout design, we can efficiently design sophisticated SoCs for your product.

Products / Services

Custom SoC (ASIC)

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Custom SoC
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Introduction Video

Socionext’s Custom SoC Solution
(YouTube)
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