Front-end Design
We offer a development environment using standard EDA tools as a SoC development environment for customers and a tool we created for improving design efficiency as a design kit. The front-end design kit, which is uniquely optimized by Socionext, enables the development of high performance, small chip size, low power LSIs.
Handoff EDA Tools
| RTL Style Check | SpyGlass Lint |
|---|---|
| Functional Verification | VCS, Xcelium, Questa |
| Power Aware Simulation | VCS NLP, Xcelium, Questa |
| Logic Synthesis | Design Compiler NXT, Genus Synthesis Solution |
| Equivalence Check | Formality, Conformal LEC (Smart LEC) |
| Netlist Check | SpyGlass Lint |
| Pre-DFT check | SpyGlass DFT |
Implementation EDA Tools
| Logic Synthesis | Fusion Compiler, Design Compiler NXT, Genus Synthesis Solution |
|---|---|
| Equivalence Check | Formality, Conformal LEC (Smart LEC) |
| JTAG, Memory BIST | tessent |
| SCAN | DFTMAX, tessent |
| ATPG | TetraMAX, tessent |
| Netlist Check | SpyGlass Lint |
| Multi Voltage Verification | VC LP, Conformal LP |
| Verilog Simulation | VCS, Xcelium |
| Place and Route | Fusion Compiler, IC Compiler II, Innovus |
| Layout Parasitic Estraction | StarRC, Quantus |
| Timing Analysis | PrimeTime, Tempus |
| Power Analysis | PrimePower, Voltus |
| Power Integrity | RedHawk, Voltus |
| Physical Verification | IC Validator |
Design Specification Interface
Designing an SoC requires not only RTL and netlist as logic design data, but the power intent, such as the SDC describing timing specifications including clock frequency, and CPF/UPF containing power supply specifications, including power gating design and multi-power/multi voltage design. We provide interface files in our unique format for such SDC and power intent. Using such files allows you to improve efficiency in writing and reviewing specifications and quickly verify the consistency between the handed-off RTL, power supply specifications, and timing specifications as well as layout compatibility.
Physical aware Logic synthesis
Due to progress in technology, logic design that takes layout into account is becoming important for improving SoC design efficiency as well as optimizing area and timing. For this reason, we adopt physical aware synthesis that performs optimization by taking the actual layout into account. Through this co-design between the logic design and layout design, we can efficiently design sophisticated SoCs for your product.
