Interface Macro

DDR Interface

Socionext provides various DDR interface macros from low-to-middle speed forwarding bandwidth to high-speed forwarding bandwidth or low power, with various process technologies. Moreover, we support development for signal quality and cost optimization through design support by Chip-Package-Board co-design.

[DDR Interface Configuration Diagram]

[DDR Interface Configuration Diagram]

DDR Interface macros

High-speed/ high-bandwidth：DDR5/DDR4/DDR3

Low Power：LPDDR5/4X/4/3/2/DDR3L

DFI compliant (all macro)

Compatible with many different DRAM configurations and PKG options, such as Fly-by, PoP, and DIMM thanks to the PHY function (training function).

DDR interface design support (Chip–Package–Board codesign)

Timing verification : Verifies the timing of all DDR-IF systems including delays between LSI I/O and DRAM

Power Integrity : Optimizes the parasitic inductance, resonant frequency, and power supply (PKG, PCB) impedance as part of the power supply impedance design

Signal Integrity : Optimizes Driver strength, terminator resistance, and interconnect topology

Bus switching verification: Optimizes write and read bus switch timing

[LPDDR4 3733 DQ Waveforms]

[LPDDR4 3733 DQ Waveforms]

[Bus Switching Waveforms]

[Bus Switching Waveforms]

Memory Controllers

Socionext provides various memory solutions for system optimization. We also offer consulting services on memory systems including memory channels and the system bus to maximize SoC performance.

Memory controller IP

Controller for maximizing high DRAM utilization

QoS-Arbiter IP

High performance QoS-Arbiter featuring multiple functions

Bus IP

Original low power consumption bus with high layout flexibility

Monitor IP

Visualizes memory system performance in real-time

Monitors performance (bandwidth, latency) and provides an environment for tuning parameters

MIPI Interface

This high-speed interface is used to build a camera and display system by combining high-speed, high resolution CMOS image sensors. This interface provides a solution for highly expressive images.

MIPI C/D-PHY macro

Transmission speed　C-PHY 3.5Gsps(8Gbps) @ 1lane

Transmission speed　D-PHY 4.5Gbps @ 1lane

C-PHY Rx reception tolerance test waveform

PCI Express Interface

As a result of the recent rapid improvement in CPU processing capability and an increase in the need for high-capacity data transfer, it has become extremely difficult to achieve the expected system performance with existing buses. The PCI Express interface used by Socionext overcomes these problems by being able to deliver data transfer rates in the hundreds of megabytes. Socionext’s PCI Express macro supports up to 8 GT/s (Gen3) and passed the PCI Express standard compliance test hosted by PCI-SIG, and its interconnectivity and reliability have been confirmed with many PCI Express interfaces.

PCI Express PHY Macro

Compliant with PCI Express Base Specification rev. 5.0

CXL 2.0 compliant

Transmission speed: Up to 32 Gbps per lane

Support for x1, x2, or x4 lanes

PIPE compliance enables connection to standard LINK interfaces

Built-in functions that support system development by customers
-Built-in bit error checker for verifying reception status
-Powerful adaptive equalizer function to easily enable optimal performance
-On-chip eye monitor for verifying transmission conditions

PCI Express Gen5 Evaluation Environment

[PCI Express Gen5 Evaluation Environment]

PCI Express Gen5 output waveform @32 Gbps

[PCI Express Gen5 output waveform @32 Gbps]

1G-56Gbps SerDes Interface

With transmission performance of 1 Gbps to 56.4 Gbps per lane and a configuration comprised of multiple channels, we provide a high-performance SerDes macro for constructing 100G/200G/400G optical networks or 100G Ether systems.
The built-in low-jitter, high-performance PLL enables robust transmission up to 28 Gbps per lane (PAM4 56 Gbps). Support is available for a wide range of standards, including OIF-CEI-11G-SR, OIF-CEI-28G-SR, OIF-CEI-28G-VSR, OIF-CEI-56G-VSR, IEEE802.3ba CAUI, IEEE802.3bm CAUI4, and XFI and so forth.

x1, x2, x4 lane configuration

Comprised of Transmitter/Receiver/PLL and capable of bidirectional communication with 1 macro

Up to 225.6 Gbps per macro (for unidirectional, x4 configuration)

Support for power-down control on each channel

Support for power-down control for the entire macro

Implementing Clock-Data recovery for each Receiver lane

Support for transmitter equalization

Support for receiver equalization

Built-in termination resistor in Transmitter/Receiver

Organic flip chip package
(0.8 mm/1.0 mm Ball Pitch, HDBU Package)