Socionext provides various DDR interface macros from low-to-middle speed forwarding bandwidth to high-speed forwarding bandwidth or low power, with various process technologies.
Moreover, we support custom SoC development by LSI-Package-Board co-design.
●DDR Interface macros
- High-speed/ high-bandwidth : DDR3/DDR4
- Low Power : LPDDR4X/4/3/2DDR3L
- DFI compliant (all macro)
- Compatible with many different DRAM configurations and PKG options, such as Fly-by and PoP thanks to the PHY function (training function).
●DDR Interface design support (LSI–Package–Board co-design)
- Timing verification : Verifies the timing of all DDR-IF systems including delays between LSI I/O and DRAM
- Power Integrity : Optimizes the parasitic inductance, resonant frequency, and power supply (PKG, PCB) impedance as part of the power supply impedance design
- Signal Integrity : Optimizes Drivers trength, terminator resistance, and interconnect topology
[DDR Interface Configuration Diagram]
[LPDDR4 3733 DQ Waveforms]
[Bus Switching Waveforms]
Socionext provides various memory solutions for system optimization. We also offer consulting services on memory systems including memory channels and the system bus to maximize SoC performance.
●Memory controller IP
- Controller for maximizing high DRAM utilization
- High performance QoS-Arbiter featuring multiple functions
- Original low power consumption bus with high layout flexibility
- Visualizes memory system performance in real-time
- Monitors performance (bandwidth, latency) and provides an environment for tuning parameters
This high-speed interface is used to build a camera and display system by combining high-speed, high resolution CMOS image sensors. This interface provides a solution for highly expressive images.
●MIPI D-PHY TX macro
Small footprint, high-performance macro with the maximum speed of 4.5 Gbps
- 4-data lane + 1-clock lane configuration
- Transmission speed: 80 Mbps to 4.5 Gbps per lane
- Equalization function
- The world’s smallest footprint
- D-PHY2.0 compliant
[D-PHY TX Output Waveforms at 4.5 Gbps]
PCI Express Interface
As a result of the recent rapid improvement in CPU processing capability and an increase in the need for high capacity data transfer, it has become extremely difficult to achieve the expected system performance with existing buses. The PCI Express technology is a high-speed interface capable of transferring several hundred megabytes of data that can overcome this issue.
Socionext’s PCI Express macro supports up to 8GT/s (Gen3) and passed the PCI Express standard compliance test hosted by the Peripheral Component Interconnect Special Interest Group (PCI-SIG), and its interconnectivity and reliability have been confirmed with many PCI Express interfaces.
[PCI Express Gen3 Evaluation Environment]
●PCI Express LINK macro
- Compliant with the PCI Express Base Specification rev.3.0 standard specification
- Support for x1, x4, and x8 lanes
- DualMode (RootComplex or Endpoint is selectable)
- Possible to select AMBA3 I/F as the user interface
- Built-in DMAC
●PCI Express PHY macro
- Maximum transfer bit rate of 64 GT/s
- High-speed signal transmission with the de-emphasis function is guaranteed
- The LINK macro interface is compliant with the PIPE3 and PIPE4 standard specifications
10G-28Gbps SerDes Interface
With transmission performance of 10Gbps–28Gbps per channel and a configuration comprised of multiple channels, we provide a high-performance SerDes macro for constructing 100G/200G/400G optical networks or 100G Ether systems. The built-in low-jitter, high-performance PLL enables robust transmission up to 28 Gbps per channel. It also supports various standards including OIF-CEI-11GSR, OIF-CEI- 28G-SR, OIF-CEI-28G-VSR, IEEE802.3ba CAUI, IEEE802.3bm CAUI4, XFI and so forth.
- x1, x4 lane configuration.
- Comprised of Transmitter/Receiver/PLL and capable of bidirectional communication with 1 macro.
- Up to 112.8 Gbps per macro (for unidirectional, x4 configuration).
- Support for power-down control on each lane.
- Support for power-down control for the entire macro.
- Implementing Clock-Data recovery for each Receiver lane.
- Transmitter Equalization supported.
- Receiver Equalization supported.
- Built-in termination resistor in Transmitter/Receiver.
- Organic flip chip package (0.8 mm/1.0 mm Ball Pitch, HDBU Package).